The present invention relates to a circuit for use with a refresh signal. In one embodiment, this circuit enables adjustment of the rate of the refresh signal in a memory device.
In dynamic random access memories (DRAMs), in order to retain data stored in memory cells, the cells are refreshed at cyclical intervals. In typical DRAM memory cells, information or data is stored as capacitor charges. These capacitive charges are subject to leakage currents. Consequently, the stored charges on the capacitors within the DRAM have to be repeatedly renewed in order to retain the charges and the data.
Typical DRAM consists of a multitude of memory cells accessible by word lines and bit lines. The memory cells are typically further divided into memory banks. The refreshing of memory contents of the memory cells in the DRAM is generally carried out word line-by-word line, or row-by-row, with an internal refresh circuit. For low power or mobile DRAM applications where small current consumption is emphasized to extend battery life, various techniques are utilized in an attempt to minimize these refresh operations, because they consume significant current.
In many present day DRAM applications, the total amount of power consumed by the application, including by the DRAM, is becoming a major consideration. This is particularly important in the market driven by mobile applications. A significant portion of the power that is consumed by the application's DRAM is during refresh operations. The DRAM's refresh operations are required to maintain the stored information in the memory cell that will otherwise be lost without refreshing. Thus, it is important that as little power as possible be consumed during the DRAM's retention mode.
A significant factor in determining the amount of power consumed by the refresh operation is the frequency of, or how often, the refresh operation must take place. Typically, the refresh rate of a DRAM must be increased during active mode relative to the rate in standby operation. Increased noise during active mode typically requires an increased refresh rate.
In most cases, refresh rate times are optimized for the active mode of the DRAM product. In this way, the refresh rate during standby is unnecessarily high. For some commodity DRAM products this does not present difficulty due to somewhat relaxed power specification in this mode. For devices where power consumption is critical, however, this presents challenges. For example, most hand-held or mobile applications require data retention during long periods of nonuse.
For this and other reasons, a need exists for the present invention.